PCI-SIG is the organization which sets the standard for PCI Express and it has released the specifications for PCI Express 2.0. The new version among others introduces twice the bandwidth between components, which in practic means a theoretic maximum at 16GB/s for 16 lanes. The reason it has pushed for launch of the 2.0 specification so soon is simply because of the increasing requirements of today’s, and the coming, graphics cards. It has also made a number of optimizations of both performance and power consumption as you can see below;
- Dynamic link speed management allows developers to control the speed at which the link is operating
- Link bandwidth notification alerts platform software (operating system, device drivers, etc) of changes in link speed and width
- Capability structure expansion increases control registers to better manage devices, slots and the interconnect
- Access control services allows for optional controls to manage peer-to-peer transactions
- Completion timeout control allows developers to define a required disable mechanism for transaction timeouts
- Function-level reset provides an optional mechanism to reset functions within a multi-function device
- Power limit redefinition enables slot power limit values to accommodate devices that consume higher power
