Detaljer kring Intels Core-arkitektur|Arkiverade nyheter|Forum|Nordichardware

Intels kommande processorarkitektur som tidigare benämnt som bland annat Conroe för desktopmarknaden har nu fått sitt officiella namn, Core. Det var på IDF 2006 under gårdagen som Intel avslöjade inte bara namnet på Core-arkitekturen utan även djupare detaljer kring processorarkitekturens uppbyggnad och hur den skiljer sig mot dagens NetBurst och Pentium M-modeller. Pentium M är numera känt som Core Duo/Core Solo och det är tydligt att Intel vill visa varifrån deras nya arkitektur fått sitt arv. Justin Rattner, tekniskt huvudansvarig på Intel, både fastställde redan ryktade features hos den nya artiketuren som avslöjade en del nya.

På TechReport har man för enkelhetens skull punktat upp det vi nu fått veta om Conroe-arkitekturen och listan ser hittills ut som följande;

A four-issue-wide, 14-stage main pipeline — This will obviously be a shorter pipeline than the 31 stages in Netburst processors, much closer to the current Pentium M and Core Duo CPUs, as expected.

Micro-fusion — Known as micro-ops fusion in the Pentium M, this allows the processor to fuse together certain types of internal “micro-ops” instructions—behind the CPU’s instruction decoder, in the RISC core—and execute them as one for more performance per clock.

Macro-fusion — This is a new one, but wasn’t explained in great detail. Presumably, the CPU will be able to fuse together certain x86 ISA instructions a la micro-ops fusion. The example given was the fusion of the compare and jump instructions.

Single-cycle execution of 128-bit SSE — Core processors will execute the entire family of 128-bit SSE instructions in a single cycle, for what Intel is calling a boost in digital media performance. Obviously, higher performance per clock in SSE instructions will accelerate a range of applications.

Shared on-chip L2 cache — The dual-core Core (ack!) processors will feature a single, unified L2 cache that should allow for efficient sharing of data between the processor cores with no need for external bus traffic for cache coherency protocol traffic between the cores. Rattner said that there would be no partitioning of the L2 cache between cores, and in the event that one core should shut itself down to save power during a period of inactivity, the other core could make use of the full L2 cache if needed.

Smarter memory access — This one seems to come around every time Intel revises its CPU, but Core will indeed include new cache prefetch algorithms, which is probably necessary for best results given the move to a shared L2 cache. Also, as we learned at the last IDF, Core will have a feature called memory disambiguation that attempts to opportunistically reorder memory loads and stores when possible in order to lower effective access latencies.

Advanced power gating — Clock gating shuts down logic on the chip when it’s not needed at the time. In his keynote speech, Intel’s Pat Gelsinger described the Core architecture’s clock gating as “super-fine grained.”

Prestanda talade man gärna om och speciellt för desktop-modellen Conroe som sades leverera upp till 40% högre prestanda med 40% mindre strömförbrukning än en Pentium D 950-processor. Om inte det är en imponerande siffror vet vi inte vad. Intel verkar onekligen vara på rätt väg med sin nya arkitektur och vi ser med spänning fram emot dess lansering senare i år.

Källa: TechReport