IBM has as we earlier reported developed the possibility to use DRAM for cache in a processor and thanks to the DRAM technology’s generous space IBM will be able to triple the memory buffer with today’s processors. But on top of its new cache technology, IBM also has other technologies coming that will further optimize the use of processor cache. Through these technologies and its new 45nm manufacturing process IBM is hoping to increase the processor cache to a whopping 48MB (!) next year. IBM’s current Power6 processor uses 8MB SRAM cache, for comparison.
“To put 24-36MB of memory on a chip, you would need a 600mm² die today. Using this technology you could put that much memory on a 300-350mm² die,” Iyer said.
IBM’s new technologies is expected to be used with both future and current Power and Cell processors, the latter which it developed together with Sony and Toshiba. Today, 8MB L2 cache sounds like a lot, but it’s nothing compared to what’s coming.
