The Quad-core Opteron is expected to arrive during the second half of 2007 and now it seems that AMD has some new plans for keeping the cores supplied with data. It has according to a roadmap published at HKEPC went for a shared L2 cache with its “Deerhound” Opteron that use AMD’s coming Socket 1207 and sport dual channel DDR2 memory. This would mean that AMD will not continue with its current design where each processor core has its own L2 cache and a shared cache would make AMD’s processors more alike Intel’s coming Core architecture that will also use a shared L2 cache. After Deerhound AMD’s “Greyhound” is expected to be launched for the stationary market and it will be the first Quad-core processor in AMD’s desktop segment.
Here we find some more news during the second half of 2008 when Greyhound is expected to arrive. The processor will just as Deerhound use 65nm technology and a shared L2 cache, but this with Socket AM3 and DDR2/DDR3 memory that are supported, together with the new HyperTransport 3.0 bus.
The HT3.0 support on the server market will come during the second half of 2008 as “Zamora” and “Cadiz”. The first is intended for multi processor platforms and this model will support FB-DIMM and a shared L3 cache.
AMD has some truly interesting plans for its desktop and server processors where Quad-core will become reality in just a year. For the desktop market it will take a bit longer though.
Source: HKEPC
