Out of practically nowhere Tilera has announced the TILE64 processor. It is a 64-core processor, where the cores are arranged in a mesh network, not entirely unlike the Terascale project Intel is working on. Tilera is quite confident about its new product and even states that it delivers ten times the performance and thirty times the performance-per-watt of an Intel dual-core Xeon. The base of the TILE64 is actually the Raw project that started back in 1996, which was backed up by DARPA and NSF. It first spawned a multi-core processor back in 2002, and some software, and has now resulted in the TILE64.
Tilera targets its processor at the embedded and digital multimedia applications and claims to have dozens of clients integrating the new processor into networking and multimedia products.
“This is the first significant new chip architectural development in a decade,” said Tilera President and C.E.O., Devesh Garg. “We developed this new architecture because existing multicore technologies simply cannot scale beyond a handful of cores. Moreover, customers have repeatedly indicated that the current multicore software tools are very primitive because they are based on single-processor-core models. We’re introducing a revolutionary hardware and software platform that has solved the fundamental challenges associated with multicore scalability.”
The cores themselves use a rather short in-order pipeline that implements a VLIW instruction set, where the L2 cache has a rather interesting feature that makes it possible for the core to check the cache of other cores for the right data, if there would happen to be a miss in the pipeline. If that fails it can always fall back on the main memory. To put it simply, the L2 cache also acts as a collective L3 cache in case of a miss in the pipeline of one of the cores.
TILE64 also has two 10Gb Ethernet interfaces, two Gigabit Ethernet interfaces, four DDR2 memory controllers and two PCIe interfaces. It also features an I/O interface that can be controlled via software to handle various protocols. TILE64 runs at speeds up to 900MHz and is made by TSMC. Tilera has chosen to use the rather old 90nm process for its first version of TILE64, most likely to keep costs down, but will (perhaps) migrate when/if the processor becomes the hit Tilera expects it to be.
