Last week Intel Developer Forum was the source of quite a lot of stories and one of the most interesting was posted over at c|net. Stephen Shankland has summarized the presentation by Pat Gelsinger, General Manager of the Digital Enterprise Group at Intel, about the Nehalem processor architecture and the interface we’ve known as CSI. Intel taped out the A0 revision of Nehalem just three weeks before IDF and had a system with two of these up and running. The system consisted of two quad-cores capable of handling two hardware threads per core, which means a total of 16 threads was processed at the same time. Later on there will be single processors with eight cores (4+4).
But the perhaps most exciting new “feature” of Nehalem is that it will use the new bus interface we’ve known as CSI (Common System Interface), but from now on shall be known as QPI (QuickPath Interface). QPI is simply Intel’s answer to AMD’s Direct Connect technology.
Thanks to the Direct Connect architecture, AMD managed to gain and secure a quite large portion of the server market as it allowed for higher transfer rates between processors and systems, and more flexibility, than the system used by Intel. Intel on the other hand could counter with more cache and higher frequencies, and they did, over and over again, but with QuickPath Intel will have an interface that is up to par with Direct Connect and still have the cache advantage.
AMD managed to create a quite solid performance advantage through the launch of Direct Connect back in 2003 with the Opteron and Athlon 64, while Intel kept pushing for higher frequencies and more cache with its NetBurst processors. Intel later made up for it through the launch of the Core architecture, but it still uses pretty much the same, but slightly faster bus architecture.
QPI will introduce two significant improvements over today’s interface. First of all it will introduce integrated memory controllers for Nehalem processors. The advantages are of course lower access times to the system memory, the disadvantage are a reduced scaling of the frequency and added complexity of the core, which means lower yields, but overall these are negligible if the manufacturing process is tuned well.
The second is more interesting for servers as it allows processors to communicate directly with each other instead through the northbridge. Two processors will be able to share information in a snap now, instead of having to go via a third chip.
Nehalem is expected to arrive in the summer of 2008 if things continue to go this well, and until then we will have to settle for Intel’s coming Penryn processors, which we hope tell you more about soon.
